9/16/2023 0 Comments Vhdl program for 2 bit alu![]() ![]() Op <= "111" wait for Clk_period -Bitwise XOR of A and B Op <= "110" wait for Clk_period -Bitwise OR of A and B Op <= "101" wait for Clk_period -Bitwise AND of A and B Op <= "100" wait for Clk_period -Bitwise NOR of A and B Op <= "011" wait for Clk_period -Bitwise NAND of A and B Op <= "010" wait for Clk_period -Bitwise NOT of A Op <= "001" wait for Clk_period -subtract B from A. Op <= "000" wait for Clk_period -add A and B Signal A,B,R : signed(31 downto 0) := (others => '0') Temp := std_logic_vector((unsigned("0" & Reg1) + unsigned(Reg2))) R : out signed(31 downto 0) -output of ALU ![]() Op : in unsigned(2 downto 0) -Operation to be performed I have been trying to work it but always get errors, still want to add proper zero flag and overflow but each time try something online I restart from scratch.Ī,B : in signed(31 downto 0) -input operands Input named Operation partially specifies the operation code. Two data inputs according to an operation code supplied to the ALU. This ALU can perform addition, subtraction, AND, OR on the ![]()
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